Application Specific Integrated Circuits (ASIC) typically include gate arrays and standard cells (CMOS, bipolar and BIMOS technology). Gate arrays are mainly pre-processed wafers with macrocells which are similar to familiar standard logic functions. A designer calls up these macrocells from a softward library on a Computer Aided Design (CAD) system and places them in the desired location with appropriate interconnections. Gate arrays provide increased silicon effieiency and consequently higher logic densities and lower cost than previously used large scale integrated (LSI) circuit design methodologies.
Standard Cells comprise a library of functions ranging from primitive functions such as AND and OR gates to more comples functions such as random access memory (RAM). The designer designs the chip by placing and interconnecting the pre-defined library of functions.
The task of verifying the boolean functionality of gate array and standard cell libraries, both from a CAD and a silicon point of view, has been difficult with previously known methodologies. The logic designer is concerned whether his design configurations are fully functional on silicon. The layout, or CAD, designer is concerned whether his library models and associated tools function correctly and thus produce functional silicon.
Three previously known methods exist for verifying functionality of gate array and standard cell libraries. A first approach ties the inputs of the macros directly to package pins (may be buffered if required by the technology). Although this is a simple design and direct access of all ports is obtained, the design is input/output intensive, requires manual test pattern development and manual verification of output response.
A second approach multiplexes the output of the macros to reduce the number of required output pins. Additional control pins are added to direct the multiplexer.
A third approach includes a binary counter for creating vectors as inputs to the macros of the library and multiplexing the outputs of the macros. This is the best of the three previously known approaches since exhaustive macro functional verification can be achieved. The limitation of this approach, as with the first two, is that the problem of stimulating sequential macros is not accomplished. These approaches do not exhaustively test sequential macros and require extra special care since timing is critical. Additionally, the task of output response verification is not satisfied.
With gate arrays and standard cell configurations growing in size and complexity, the need for tools and design configurations for verifying these environments, in a timely fashion, are of utmost importance.
Thus, what is needed is a design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells of Application Specific Integrated Circuit gate array and standard cell libraries.